TH58NVG1S3AFT05 Datasheet | Toshiba

TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2GBIT (256M u 8BITS) CMOS NAND E2PROM DESCRIPTION The TH58NVG1S3A is a single 3.3-V 2G-bit (2,214,592,512 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048+64) bytes x 64 pages x 2048 blocks. The device has a 2112-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes + 4Kbytes: 2112 bytes x 64 pages). The TH58NVG1S3A is a serial-type memory device which utilizes the I/O pins for both address and data input / output as well as for mand inputs. The Erase and Program operations are automatically executed making the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and other systems which require high-density nonvolatile memory data storage. Features x Organization Memory cell allay 2112 u 64K u 8 u 2 Register 2112 u 8 Page size 2112bytes Block size (128K 4K) bytes x Modes Read㧘Reset㧘Auto Page Program Auto Block Erase㧘Status Read x Mode control Serial input㧛output mand control x Powersupply x Program/Erase Cycles x Access time Cell array to register Serial Read Cycle x Operating current Read (50 ns cycle) Program (avg.) Erase (avg.) Standby x Package TSOP I 48-P-1220-0.50 (Weight : 0.53 g typ.) VCC 2.7 V to 3.6 V 1E5 Cycles(With ECC) 25 Psmax 50 ns min 10 m A typ. 10 m A typ. 10 m A typ. 50 PA max PIN ASSIGNMENT (TOP VIEW) NC NC NC NC NC GND RY/BY RE CE NC NC VCC VSS NC NC CLE ALE WE WP NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC I/O8 I/O7 I/O6 I/O5 NC NC NC VCC VSS NC NC NC I/O4 I/O3 I/O2 I/O1 NC NC NC NC PIN NAMES I/O1 to I/O8 I/O port WE RE CLE ALE WP RY / BY...