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TH58NVG5S0FTAK0 - 32 GBIT (4G x 8 BIT) CMOS NAND E2PROM

Datasheet Summary

Description

The TH58NVG5S0F is a single 3.3V 32 Gbit (36,305,895,424 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (4096 + 232) bytes × 64 pages × 16384 blocks.

Features

  • Organization x8 Memory cell array 4328 × 256K × 8 × 4 Register 4328 × 8 Page size 4328 bytes Block size (256K + 14.5K) bytes.
  • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Program, Multi Block Erase, Multi Page Copy, Multi Page Read.
  • Mode control Serial input/output Command control.
  • Number of valid blocks Min 16064 blocks Max 16384 blocks.
  • Power supply VCC = 2.7V to 3.6V.
  • Access time.

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Datasheet Details

Part number TH58NVG5S0FTAK0
Manufacturer Toshiba Semiconductor
File Size 935.53 KB
Description 32 GBIT (4G x 8 BIT) CMOS NAND E2PROM
Datasheet download datasheet TH58NVG5S0FTAK0 Datasheet
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TH58NVG5S0FTAK0 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM DESCRIPTION The TH58NVG5S0F is a single 3.3V 32 Gbit (36,305,895,424 bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (4096 + 232) bytes × 64 pages × 16384 blocks. The device has two 4328-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 4328-byte increments. The Erase operation is implemented in a single block unit (256 Kbytes + 14.5 Kbytes: 4328 bytes × 64 pages). The TH58NVG5S0F is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.
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