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TOSHIBA
Toshiba’s 1 Mbit embedded DRAM core is available for the TC220C and TC220E product families. Each DRAM cell is based on a three transistor structure as shown in Figure 1. This multi-feature DRAM core is easily integrated into a broad range of applications through utilization of different core configurations.
w DRAM Core Features w
• Power supply: 3.3V ±0.3V • Memory configurations – 128K x 8 bit – 64K x 16 bit – 32K x 32 bit – 16K x 64 bit • Full address without multiplex • Separate data input and output • Read access modes – Random access – EDO/Hyper page mode • Refresh scheme – RAS only refresh – CBR (CAS before RAS) refresh • Performance specification – trc random read cycle: 50 ns – tpc page mode read cycle: 25 ns – Refresh cycle: 256 cycles/ms (@Tj = 85°C)
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TC220C Datasheet
