Datasheet4U Logo Datasheet4U.com

TC58NS100DC Datasheet 1 Gbit CMOS Nand Eprom

Manufacturer: Toshiba

Overview: TC58NS100DC TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 TM 1-GBIT (128M × 8 BITS) CMOS NAND E PROM (128M BYTE.

General Description

) The TC58NS100 is a single 3.3-V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as 528 bytes × 32 pages × 8192 blocks.

The device has a 528-byte static register which allows program and read data to be transferred between the register and the memory cell array in 528-byte increments.

The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes × 32 pages).

Key Features

  • Organization Memory cell array 528 × 256K × 8 Register 528 × 8 Page size 528 bytes Block size (16K + 512) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read Mode control Serial input/output, Command control Complies with the SmartMediaTM Electrical Specification and Data Format Specification issued by the SSFDC Forum.
  • Power supply VCC = 3.3 V ± 0.3 V Program/Erase Cycles 1E5 cycle (with ECC) Access time Cell array-register 2.

More Datasheets from Toshiba

Part Number Description
TC58NS128BDC 128 MBit CMOS NAND EPROM
TC58NS256BDC 256 MBit CMOS NAND EPROM
TC58NS512ADC 512 MBit CMOS NAND EPROM
TC58NS512DC 512 MBit CMOS NAND EPROM
TC58NVG0S3AFT00 1 GBit CMOS NAND EPROM
TC58NVG0S3AFT05 1 GBit CMOS NAND EPROM
TC58NVG0S3ETA00 1 GBIT (128M X 8 BIT) CMOS NAND E2PROM
TC58NVG0S3HBAI4 1G BIT (128M x 8-BIT) CMOS NAND E2PROM
TC58NVG0S3HBAI6 1G-BIT (128M x 8 BIT) CMOS NAND E2PROM
TC58NVG0S3HTA00 1 GBIT (128M x 8 BIT) CMOS NAND E2PROM

TC58NS100DC Distributor