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TC58NVG0S3HBAI4 - 1G BIT (128M x 8-BIT) CMOS NAND E2PROM

General Description

The TC58NVG0S3HBAI4 is a single 3.3V 1Gbit (1,140,850,688bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048  128) bytes  64 pages  1024blocks.

Key Features

  • Organization Memory cell array Register Page size Block size.
  • x8 2176  64K  8 2176  8 2176 bytes (128K  8K) bytes Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy Mode control Serial input/output Command control Number of valid blocks Min 1004 blocks Max 1024 blocks Power supply VCC  2.7V to 3.6V Access time Cell array to register 25 s max Serial Read Cycle 25 ns min (CL=50pF) Program/Erase time Auto Page Program Auto Block Erase Operating cu.

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Datasheet Details

Part number TC58NVG0S3HBAI4
Manufacturer Toshiba
File Size 671.57 KB
Description 1G BIT (128M x 8-BIT) CMOS NAND E2PROM
Datasheet download datasheet TC58NVG0S3HBAI4 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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TC58NVG0S3HBAI4 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 1G BIT (128M  8 BIT) CMOS NAND E PROM DESCRIPTION The TC58NVG0S3HBAI4 is a single 3.3V 1Gbit (1,140,850,688bits) NAND Electrically Erasable and Programmable Read-Only Memory (NAND E2PROM) organized as (2048  128) bytes  64 pages  1024blocks. The device has a 2176-byte static registers which allow program and read data to be transferred between the register and the memory cell array in 2176-byte increments. The Erase operation is implemented in a single block unit (128 Kbytes  8 Kbytes: 2176 bytes  64 pages). The TC58NVG0S3HBAI4 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for command inputs.