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TH58BVG3S0HTAI0 Datasheet

Manufacturer: Toshiba
TH58BVG3S0HTAI0 datasheet preview

Datasheet Details

Part number TH58BVG3S0HTAI0
Datasheet TH58BVG3S0HTAI0-Toshiba.pdf
File Size 691.58 KB
Manufacturer Toshiba
Description 8 GBIT (1G x 8 BIT) CMOS NAND E2PROM
TH58BVG3S0HTAI0 page 2 TH58BVG3S0HTAI0 page 3

TH58BVG3S0HTAI0 Overview

The device has a 4224-byte static register which allows program and read data to be transferred between the register and the memory cell array in 4224-bytes increments. The Erase operation is implemented in a single block unit (256 Kbytes + 8 Kbytes: The TH58BVG3S0HTAI0 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as well as for mand inputs.

TH58BVG3S0HTAI0 Key Features

  • Organization
  • Modes Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, Multi Page Read, Multi Page Program, Mul
  • Mode control Serial input/output mand control
  • Number of valid blocks Min 4016 blocks Max 4096 blocks
  • Power supply VCC = 2.7V to 3.6V
  • Access time Cell array to register 55 µs typ. (Single Page Read) / 90µs typ. (Multi Page Read) Serial Read Cycle 25 ns m
  • Program/Erase time Auto Page Program Auto Block Erase
  • Operating current Read (25 ns cycle) Program (avg.) Erase (avg.) Standby
  • Package TSOP I 48-P-1220-0.50 (Weight: 0.54 g typ.)
  • 8bit ECC for each 528Byte is implemented on the chip
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