SI1473DH Datasheet | Vishay

DESCRIPTION .. The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a mercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74371 S-70349Rev. A, 26-Feb-07 .vishay. 1 SPICE Device Model Si1473DH Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 2.2 55 0.085 0.118 3 - 0.84 Measured Data Unit VGS(th) ID(on) r DS(on) gfs VSD VDS = VGS, ID = - 250 µA VDS ≤ - 5 V, VGS = - 10 V VGS = - 10 V, ID = - 2 A VGS = - 4.5 V, ID = - 1.6 A VDS = - 10 V, ID = - 2 A IS = - 2 A V A 0.084 0.120 6 - 0.85 Ω S V Drain-Source On-State Resistancea Forward Transconductancea .. Diode Forward Voltagea Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Ciss Coss Crss Qg Qgs Qgd VDS = - 15 V, VGS = - 4.5 V, ID = - 2.5 A VDS = - 15 V, VGS = 0 V, f = 1 MHz 436 69 51 4.1 1.2 1.7 365 68 51 4.1 1.2 1.7 n C p F Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. .vishay....