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WED2ZL361MS - Synchronous Pipeline Burst NBL SRAM

General Description

The WEDC SyncBurst - SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process.

WEDC’s 32Mb SyncBurst SRAMs integrate two 1M x 18 SRAMs into a single BGA package to provide 1M x 36 configuration.

Key Features

  • Fast clock speed: 250, 225, 200, 166, 150, 133MHz Fast access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns Fast OE# access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns Separate +2.5V ± 5% power supplies for Core, I/O (VCC, VCCQ) Snooze Mode for reduced-standby power Individual Byte Write control Clock-controlled and registered addresses, data I/Os and control signals Burst control (interleaved or linear burst) Packaging:.
  • 119-bump BGA package Lo.

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Datasheet Details

Part number WED2ZL361MS
Manufacturer White Electronic
File Size 673.25 KB
Description Synchronous Pipeline Burst NBL SRAM
Datasheet download datasheet WED2ZL361MS Datasheet

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www.DataSheet4U.com White Electronic Designs 1Mx36 Synchronous Pipeline Burst NBL SRAM FEATURES           Fast clock speed: 250, 225, 200, 166, 150, 133MHz Fast access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns Fast OE# access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns Separate +2.5V ± 5% power supplies for Core, I/O (VCC, VCCQ) Snooze Mode for reduced-standby power Individual Byte Write control Clock-controlled and registered addresses, data I/Os and control signals Burst control (interleaved or linear burst) Packaging:  119-bump BGA package Low capacitive bus loading WED2ZL361MS DESCRIPTION The WEDC SyncBurst - SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process.