WED2ZL361MS Datasheet PDF - White Electronic Synchronous Pipeline Burst NBL SRAM Specs

Datasheet Details

Part number	WED2ZL361MS
Manufacturer	White Electronic
File Size	673.25 KB
Description	Synchronous Pipeline Burst NBL SRAM
Datasheet	WED2ZL361MS Datasheet
Additional preview pages of the WED2ZL361MS datasheet.

WED2ZL361MS Product details

The WEDC SyncBurst - SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process.

WEDC’s 32Mb SyncBurst SRAMs integrate two 1M x 18 SRAMs into a single BGA package to provide 1M x 36 conﬁguration.

Fast clock speed: 250, 225, 200, 166, 150, 133MHz Fast access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns Fast OE# access times: 2.6, 2.8, 3.0, 3.5, 3.8, 4.2ns Separate +2.5V ± 5% power supplies for Core, I/O (VCC, VCCQ) Snooze Mode for reduced-standby power Individual Byte Write control Clock-controlled and registered addresses, data I/Os and control signals Burst control (interleaved or linear burst) Packaging:.
119-bump BGA package Lo.

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