WED2ZL361MV Datasheet PDF - White Electronic Synchronous Pipeline Burst NBL SRAM Specs

Datasheet Details

Part number	WED2ZL361MV
Manufacturer	White Electronic
File Size	357.45 KB
Description	Synchronous Pipeline Burst NBL SRAM
Datasheet	WED2ZL361MV Datasheet
Additional preview pages of the WED2ZL361MV datasheet.

WED2ZL361MV Product details

The WEDC SyncBurst

SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process.

WEDC’s 32Mb SyncBurst SRAMs integrate two 1M x 18 SRAMs into a single BGA package to provide 1M x 36 conﬁguration.

Fast clock speed: 166, 150, 133, and 100MHz Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns Single +3.3V ± 5% power supply (VCC) Snooze Mode for reduced-standby power Individual Byte Write control Clock-controlled and registered addresses, data I/Os and control signals Burst control (interleaved or linear burst) Packaging:.
119-bump BGA package Low capacitive bus loading This product is subject to change without notice. WED2ZL361M.

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