WED2ZL361MV Overview
The WEDC SyncBurst SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 32Mb SyncBurst SRAMs integrate two 1M x 18 SRAMs into a single BGA package to provide 1M x 36 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK).
WED2ZL361MV Key Features
- 119-bump BGA package Low capacitive bus loading
- SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. WEDC’s 32Mb Sy