WED2ZLRSP01S Overview
The WED2ZLRSP01S, Dual Independent Array, NBLSSRAM device employs high-speed, Low-Power CMOS silicon and is fabricated using an advanced CMOS process. WEDC’s 24Mb, Sync Burst SRAM MCP integrates two totally independent arrays, the first organized as a 512K x 32, and the second a 256K x 32. All Synchronous inputs pass through registers controlled by a positive edge triggered, single clock input per array.