Description
D0-31 A0-18 SWE#1-4 SCS# OE# VCC GND NC FWE#1-4 FCS Data Inputs/Outputs Address Inputs SRAM Write Enables SRAM Chip Select Output Enable Power Supply Ground Not Connected Flash Write Enables Flash Chip Select
56
Block Diagram
FWE 1 # SWE 1 # FWE 2 # SWE 2 # FWE 3 # SWE 3 # FWE 4 # SWE 4 #
128K x
Features
- Access times of 25ns (SRAM) and 120ns (FLASH) Packaging.
- 66 pin, PGA Type, 1.385" square HIP, hermetic ceramic HIP (Package 402).
- 68 lead, hermetic CQFP (G2T), 22.4mm (0.880") square (Package 509) 4.57mm (0.180") height Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (FIGURE 2). Package to be developed. 128Kx32 SRAM 512Kx32 5V Flash Organized as 128Kx32 of SRAM and 512Kx32 of Flash Memory with common data bus Low power CMOS Commercial, industrial and military temperature ran.
WSF41632-22XX Datasheet
