W955K8MBYA Description
Bus transactions are initiated with a High to Low transition. Bus transactions are terminated with a Low to High transition. The master device has a separate CS# for each slave.
W955K8MBYA Key Features
- Interface: HyperBus
- Power supply: 1.7V~2.0V
- Maximum clock rate: 200MHz
- Double-Data Rate (DDR) Up to 400 MT/s
- Single ended clock (CK)
- Differential clock (CK/CK#)
- Chip Select (CS#)
- 8-bit data bus (DQ[7:0])
- Hardware reset (RESET#)
- Read-Write Data Strobe (RWDS)