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XC2C64A - CoolRunner-II CPLD

General Description

The CoolRunner-II 64-macrocell device is designed for both high performance and low power applications.

This lends power savings to high-end communication equipment and high speed to battery operated devices.

Key Features

  • Optimized for 1.8V systems - As fast as 4.6 ns pin-to-pin logic delays - As low as 15 μA quiescent current.
  • Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation.
  • 1.5V to 3.3V.
  • Available in multiple package options - 44-pin VQFP with 33 user I/Os - 48-land QFN with 37 user I/Os - 56-ball CP BGA with 45 user I/Os - 100-pin VQFP with 64 user I/Os - Pb-free available for all packages.

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Full PDF Text Transcription for XC2C64A (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for XC2C64A. For precise diagrams, and layout, please refer to the original PDF.

0 R XC2C64A CoolRunner-II CPLD DS311 (v2.3) November 19, 2008 0 0 Product Specification Features • Optimized for 1.8V systems - As fast as 4.6 ns pin-to-pin logic delays ...

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ptimized for 1.8V systems - As fast as 4.6 ns pin-to-pin logic delays - As low as 15 μA quiescent current • Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation — 1.5V to 3.3V • Available in multiple package options - 44-pin VQFP with 33 user I/Os - 48-land QFN with 37 user I/Os - 56-ball CP BGA with 45 user I/Os - 100-pin VQFP with 64 user I/Os - Pb-free available for all packages • Advanced system features - Fastest in system programming · 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.