Datasheet Summary
R XC2C32A CoolRunner-II CPLD
DS310 (v2.1) November 6, 2008
0 0 Product Specification
Features
- Optimized for 1.8V systems
- As fast as 3.8 ns pin-to-pin logic delays
- As low as 12 μA quiescent current
- Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis
- Multi-voltage I/O operation: 1.5V through 3.3V
- Available in multiple package options
- 32-land QFN with 21 user I/Os
- 44-pin VQFP with 33 user I/Os
- 56-ball CP BGA with 33 user I/Os
- Pb-free available for all packages
- Advanced system Features
- Fastest in system programming
- 1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger...