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XC2C32A - CoolRunner-II CPLD

General Description

The CoolRunner™-II 32-macrocell device is designed for both high performance and low power applications.

This lends power savings to high-end communication equipment and high speed to battery operated devices.

Key Features

  • Optimized for 1.8V systems - As fast as 3.8 ns pin-to-pin logic delays - As low as 12 μA quiescent current.
  • Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation: 1.5V through 3.3V.
  • Available in multiple package options - 32-land QFN with 21 user I/Os - 44-pin VQFP with 33 user I/Os - 56-ball CP BGA with 33 user I/Os - Pb-free available for all packages.
  • Advanced system features - Fastest in.

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XC2C384 CoolRunner-II CPLD
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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0 R XC2C32A CoolRunner-II CPLD DS310 (v2.1) November 6, 2008 0 0 Product Specification Features • Optimized for 1.8V systems - As fast as 3.8 ns pin-to-pin logic delays - As low as 12 μA quiescent current • Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage I/O operation: 1.5V through 3.3V • Available in multiple package options - 32-land QFN with 21 user I/Os - 44-pin VQFP with 33 user I/Os - 56-ball CP BGA with 33 user I/Os - Pb-free available for all packages • Advanced system features - Fastest in system programming · 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.