Datasheet Summary
R XC2C256 CoolRunner-II CPLD
DS094 (v3.2) March 8, 2007
Features
- Optimized for 1.8V systems
- As fast as 5.7 ns pin-to-pin delays
- As low as 13 μA quiescent current
- Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis. Refer to the CoolRunner™-II family data sheet for architecture description.
- Multi-voltage I/O operation
- 1.5V to 3.3V
- Available in multiple package options
- 100-pin VQFP with 80 user I/O
- 144-pin TQFP with 118 user I/O
- 132-ball CP (0.5mm) BGA with 106 user I/O
- 208-pin PQFP with 173 user I/O
- 256-ball FT (1.0mm) BGA with 184 user I/O
- Pb-free available for all packages
- Advanced system Features
- Fastest in...