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XC2C256 Datasheet PDF

Xilinx XC2C256

The CoolRunner™-II 256-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices.
Part No. XC2C256
Datasheet XC2C256 Download
Manufacturer
Xilinx
Description CoolRunner-II CPLD
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XC2C256 datasheet page 1 preview

FEATURES

● Optimized for 1.8V systems - As fast as 5.7 ns pin-to-pin delays - As low as 13 μA quiescent current
● Industry’s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis. Refer to the CoolRunner™-II family data sheet for architecture description. - Multi-voltage I/O operation — 1.5V to 3.3V
● Available in multiple package options - 100-pin VQFP with 80 user I/O - 144-pin TQFP with 118 user I/O - 132-ball CP (0.5mm) BGA with 106 user I/O - 208-pin PQFP with 173 user I/O - 256-ball FT (1.0mm) BGA with 184 user I/O - Pb-free available for all packages
● Advanced system features - Fastest in system programming
● 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE1149.1 JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management
● DataGATE enable (DGE) signal control - Two separate I/O banks - RealDigital 100% CMOS product term generation - Flexible clocking modes
● Optional DualEDGE triggered registers
● Clock divi...
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