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XC95288XL - High Performance CPLD

Datasheet Summary

Features

  • 6 ns pin-to-pin logic delays.
  • System frequency up to 208 MHz.
  • 288 macrocells with 6,400 usable gates.
  • Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 256-pin BGA (192 user I/O pins) - 256-pin FBGA (192 user I/O pins) - 280-pin CSP (192 user I/O pins) - Pb-free available for all packages.
  • Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5V, 3.3.

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Datasheet preview – XC95288XL

Datasheet Details

Part number XC95288XL
Manufacturer Xilinx
File Size 222.46 KB
Description High Performance CPLD
Datasheet download datasheet XC95288XL Datasheet
Additional preview pages of the XC95288XL datasheet.

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Full PDF Text Transcription

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0 R XC95288XL High Performance CPLD DS055 (v2.1 April 3, 2007 05 Features • 6 ns pin-to-pin logic delays • System frequency up to 208 MHz • 288 macrocells with 6,400 usable gates • Available in small footprint packages - 144-pin TQFP (117 user I/O pins) - 208-pin PQFP (168 user I/O pins) - 256-pin BGA (192 user I/O pins) - 256-pin FBGA (192 user I/O pins) - 280-pin CSP (192 user I/O pins) - Pb-free available for all packages • Optimized for high-performance 3.3V systems - Low power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.
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