XC95288XL Description
0 R XC95288XL High Performance CPLD DS055 (v2.1 April 3, 2007.
XC95288XL Key Features
- 6 ns pin-to-pin logic delays
- System frequency up to 208 MHz
- 288 macrocells with 6,400 usable gates
- Available in small footprint packages
- 144-pin TQFP (117 user I/O pins)
- 208-pin PQFP (168 user I/O pins)
- 256-pin BGA (192 user I/O pins)
- 256-pin FBGA (192 user I/O pins)
- 280-pin CSP (192 user I/O pins)
- Pb-free available for all packages