ZL30107 - GbE Line Card Synchronizer

Reference Inputs (LVCMOS, Schmitt Trigger).

These reference inputs are used for synchronizing the PLL.

These pins are internally pulled down to Vss.

• Single chip low cost solution for synchronizing an Ethernet PHY to a standard telecom clock Generates an IEEE 802.3 jitter compliant 25 MHz Gigabit Ethernet output clock Supports three modes of operation: Asynchronous Freerun, Synchronous, and Asynchronous Holdover Defaults in Asynchronous Freerun mode In Asynchronous Freerun mode, the DPLL generates an output clock with a frequency accuracy equal to frequency accuracy of the external crystal oscillator (XO) or a lo.