ZL30109 Description
The ZL30109 DS1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk DS1 and E1 transmission equipment. The 19.44 MHz output makes the ZL30109 also suitable for SDH line card applications. The ZL30109 generates a 19.44 MHz clock and ST-BUS and TDM bus clocks and framing signals that are phase locked to one of two input references.
ZL30109 Key Features
- Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E
- Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces
- Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
- Simple hardware control interface
- Accepts two input references and synchronizes to any bination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 M
- Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz, 19.44 MHz and either 4.096 MHz and 8.192 MHz or 32.
- Hitless reference switching between any bination of valid input reference frequencies
- Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse
- Holdover frequency accuracy of 1.5 x 10-7
- Lock, Holdover and selectable Out of Range indication
ZL30109 Applications
- Synchronization and timing control for DSLAM, Gateway and PBX systems that require Stratum 4/4E timing
- Line Card synchronization for SDH/PDH applications
- Clock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) buses