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A3V28S40JTP - 128M Single Data Rate Synchronous DRAM

Datasheet Summary

Description

A3V28S40JTP is organized as 4-bank x 2,097,154-word x 16-bit Synchronous DRAM with LVTTL interface.

All inputs and outputs are referenced to the rising edge of CLK.

Features

  • - Single 3.3V ±0.3V power supply - Maximum clock frequency : - 60:166MHz/-70:143MHz/-75:133MHz - Fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/FP (programmable) - Burst type- Sequential and interleave burst (programmable) - Byte Control- LDQM and UDQM (A3V28S40JTP) - Random column access - Auto precharge / All bank precharge controlled by A10 - Su.

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Datasheet Details

Part number A3V28S40JTP
Manufacturer Zentel
File Size 945.93 KB
Description 128M Single Data Rate Synchronous DRAM
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A3V28S40JTP 128M Single Data Rate Synchronous DRAM 128Mb Synchronous DRAM Specification A3V28S40JTP Zentel Electronics Corp. Revision 1.0 Oct., 2013 A3V28S40JTP 128M Single Data Rate Synchronous DRAM General Description A3V28S40JTP is organized as 4-bank x 2,097,154-word x 16-bit Synchronous DRAM with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. A3V28S40JTP achieve very high speed data rates up to 166MHz, and are suitable for main memories or graphic memories in computer systems. Features - Single 3.3V ±0.
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