74AC11478 Datasheet | Texas Instruments

description 74AC11478 OCTAL DUAL-RANK D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCAS182 - APRIL 1989 - REVISED APRIL 1993 DW OR NT PACKAGE (TOP VIEW) 1Q 2Q 3Q 4Q GND GND GND GND 5Q 6Q 7Q 8Q 1 2 3 4 5 6 7 8 9 10 11 12 24 OE 23 1D 22 2D 21 3D 20 4D 19 VCC 18 VCC 17 5D 16 6D 15 7D 14 8D 13 CLK The 74AC11478 is an 8-bit dual-rank synchronizer circuit designed specifically for data synchronization applications in which the normal setup and hold time specifications are frequently violated. Synchronization of two digital signals operating at different frequencies is a mon system problem. This problem is typically solved by synchronizing one of the signals to the local clock through a flip-flop. This solution, however, causes the setup and hold time specifications associated with the flip-flop to be violated. When the setup or hold time of a flip-flop is violated, the output response is uncertain. A flip-flop is metastable if its output hangs up in the region between VIL and VIH. The metastable condition lasts until the flip-flop recovers into one of its two stable states. With conventional flip-flops, this recovery time can be longer than the specified maximum propagation delay. The problem of metastability is typically solved by adding an additional layer of synchronization. This dual-rank approach is employed in the 74AC11478. The probability of the second stage entering the metastable state is exponentially reduced by this dual-rank architecture. The 74AC11478 provides a one-chip solution for system designers in asynchronous applications. The 74AC11478 is characterized for operation from - 40°C to 85°C. FUNCTION TABLE INPUTS OE CLK† D OUTPUT Q L↑L L↑H Q0 † Data presented at the D inputs requires two clock cycles to appear at the Q outputs. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard...