74SSTUB32864A Datasheet | Texas Instruments

.ti. 25-BIT CONFIGURABLE REGISTERED BUFFER SCAS838 - OCTOBER 2006 Features - Member of the Texas Instruments Widebus+™ Family - Pinout Optimizes DDR2 DIMM PCB Layout - Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer - Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption - Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line - Supports SSTL_18 Data Inputs - Differential Clock (CLK and CLK) Inputs - Supports LVCMOS Switching Levels on the Control and RESET Inputs - RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low DESCRIPTION This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads. All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the open-drain error (QERR) output. The 74SSTUB32864A operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins. In the DDR2 RDIMM application, RESET is specified to be pletely asynchronous with respect to CLK...