74SSTUB32866A - 25-Bit Configurable Registered Buffer

Description

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation.

In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads.

In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.

1.
2 Member of the Texas Instruments Widebus+™ Family.
Pinout Optimizes DDR2 DIMM PCB Layout.
Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer.
Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption.
Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line.
Supports SSTL_18 Data Inputs.
Differential Clock (CLK and CLK) Inputs.
Supports LVCMOS Switc.

Texas Instruments

Part number	74SSTUB32866A
Manufacturer	Texas Instruments
File Size	1.89 MB
Description	25-Bit Configurable Registered Buffer
Datasheet	74SSTUB32866A Datasheet
Additional preview pages of the 74SSTUB32866A datasheet.

74S00 - QUAD 2-input NAND GATE (ETC)
74S04 - HEX INVERTING GATES (National Semiconductor)
74S08 - Quad 2-Input AND Gate (Fairchild Semiconductor)
74S08 - Quad 2-Input AND Gates (National Semiconductor)
74S08N - Quad 2-Input AND Gate (Fairchild Semiconductor)
74S10 - STTL type three 3-input NAND gate (TW)
74S112 - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop (Fairchild Semiconductor)
74S133 - 13-Input NAND Gate (SYC)
74S134 - 12-INPUT POSITIVE-NAND GATES (Fairchild)
74S134 - 12-INPUT POSITIVE-NAND GATES (Signetics)

Other Datasheets by Texas Instruments

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74SSTUB32866A www.ti.

Published: Dec 29, 2020 |