CDC351I Description
The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V VCC.
CDC351I Key Features
- Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation