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LP2996A - Termination Regulator

Download the LP2996A datasheet PDF. This datasheet also covers the LP2996-N variant, as both devices belong to the same termination regulator family and are provided as variant models within a single manufacturer datasheet.

General Description

The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM.

The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V.

Key Features

  • 1 Minimum VDDQ:.
  • 1.8 V (LP2996-N).
  • 1.35 V (LP2996A).
  • Source and Sink Current.
  • Low Output Voltage Offset.
  • No External Resistors Required for Setting Output Voltage.
  • Linear Topology.
  • Suspend to Ram (STR) Functionality.
  • Stable With Ceramic Capacitors With Appropriate ESR.
  • Low External Component Count.
  • Thermal Shutdown 2.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (LP2996-N-etcTI.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Product Folder Sample & Buy Technical Documents Tools & Software Support & Community Reference Design LP2996-N, LP2996A SNOSA40K – NOVEMBER 2002 – REVISED DECEMBER 2016 LP2996-N, LP2996A DDR Termination Regulator 1 Features •1 Minimum VDDQ: – 1.8 V (LP2996-N) – 1.