LP2996M
Features
- 1 Minimum VDDQ:
- 1.8 V (LP2996-N)
- 1.35 V (LP2996A)
- Source and Sink Current
- Low Output Voltage Offset
- No External Resistors Required for Setting Output
Voltage
- Linear Topology
- Suspend to Ram (STR) Functionality
- Stable With Ceramic Capacitors With Appropriate
- Low External ponent Count
- Thermal Shutdown
2 Applications
- LP2996-N: DDR1 and DDR2 Termination Voltage
- LP2996A: DDR1, DDR2, DDR3, and DDR3L
Termination Voltage
- FPGA
- Industrial and Medical PC
- SSTL-2 and SSTL-3 Termination
- HSTL Termination
3 Description
The LP2996-N and LP2996A linear regulators are designed to meet the JEDEC SSTL-2 specifications for termination of DDR-SDRAM. The device also supports DDR2, while LP2996A supports DDR3 and DDR3L VTT bus termination with VDDQ minimum of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5-A continuous current and transient...
