SN55LVDS32-SP Datasheet | Texas Instruments

FEATURES - QML-V Qualified, SMD 5962-97621 - Operate From a Single 3.3-V Supply - Designed for Signaling Rates of up to 100 Mbps - Differential Input Thresholds ±100 m V Max - Typical Propagation Delay Times of 2.1 ns - Power Dissipation 60 m W Typical Per Receiver at Maximum Data Rate - Bus-Terminal ESD Protection Exceeds 8 k V - Low-Voltage TTL (LVTTL) Logic Input Levels - Open-Circuit Fail-Safe - Cold Sparing for Space and High Reliability Applications Requiring Redundancy J OR W PACKAGE (TOP VIEW) DESCRIPTION The SN55LVDS32 is a differential line receiver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four differential receivers provides a valid logical output state with a ±100-m V differential input voltage within the input mon-mode voltage range. The input mon-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. The intended application of these devices and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer depends on the attenuation characteristics of the media and the noise coupling to the environment. The SN55LVDS32 is characterized for operation from - 55°C to 125°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas...