SN55LVDS32 Datasheet | Texas Instruments

Features - 1 Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard - Operate With a Single 3.3-V Supply - Designed for Signaling Rates of up to 150 Mbps (See ) - Differential Input Thresholds ±100 m V Max - Typical Propagation Delay Time of 2.1 ns - Power Dissipation 60 m W Typical Per Receiver at Maximum Data Rate - Bus-Terminal ESD Protection Exceeds 8 k V - Low-Voltage TTL (LVTTL) Logic Output Levels - Pin patible With AM26LS32, MC3486, and μA9637 - Open-Circuit Fail-Safe - Cold Sparing for Space and High-Reliability Applications Requiring Redundancy 2 Applications - Wireless Infrastructure - Tele Infrastructure - Printer 3 Description The SN55LVDS32, SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 devices are differential line receivers that implement the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the differential receivers provides a valid logical output state with a ±100-m V differential input voltage within the input mon-mode voltage range. The input mon-mode voltage range allows 1 V of ground potential difference between two LVDS nodes. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) LCCC (20) 8.89 mm × 8.89 mm CDIP (16) 19.56 mm × 6.92 mm CFP (16) 10.30 mm × 6.73 mm SOIC (16) 9.90 mm × 3.91 mm SN65LVDS32 SOP (16) 10.30 mm × 5.30 mm TSSOP (16) 5.50 mm × 4.40 mm SN65LVDS3486 SOIC (16) TSSOP...