SN65DSI96 Overview
Key Specifications
Description
LEFT/RIGHT Operating Modes - 1.2V Main VCC Power Supply and 1.8V supply for Digital I/Os - Low Power Features Include Panel Refresh and MIPIĀ® Ultra-Low Power State (ULPS) Support - DisplayPort Lane Polarity and assignment configurable. Supports 12MHz, 19.2MHz, 26MHz, 27MHz, and The SN65DSI86/96 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPIĀ® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1.5Gbps per lane; a maximum input bandwidth of 12Gbps.