SN65LV1224 Description
The SN65LV1023 serializer and SN65LV1224 deserializer prise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 30 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 360-Mbps and 792-Mbps payload encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode...
SN65LV1224 Key Features
- 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock
- Pin-patible Superset of NSM DS92LV1023/DS92LV1224
- Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
- Synchronization Mode for Faster Lock
- Lock Indicator
- No External ponents Required for PLL
- Low-Cost 28-Pin SSOP Package
- Industrial Temperature Qualified
- Programmable Edge Trigger on Clock
- Flow-Through Pinout for Easy PCB Layout