SN65LV1224 Overview
Key Specifications
Package: VQFN
Pins: 32
Operating Voltage: 3.3 V
Max Voltage (typical range): 3.6 V
Description
The SN65LV1023 serializer and SN65LV1224 deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 30 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 360-Mbps and 792-Mbps payload encoded throughput.
Key Features
- 300-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 30-MHz to 66-MHz System Clock
- Pin-Compatible Superset of NSM DS92LV1023/DS92LV1224
- Synchronization Mode for Faster Lock
- Lock Indicator
- No External Components Required for PLL
