SN65LV1224B Datasheet | Texas Instruments

FEATURES - 100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 66-MHz System Clock - Pin-patible Superset of DS92LV1023/DS92LV1224 - Chipset (Serializer/Deserializer) Power Consumption <450 m W (Typ) at 66 MHz - Synchronization Mode for Faster Lock - Lock Indicator - No External ponents Required for PLL - 28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available - Industrial Temperature Qualified, TA = - 40°C to 85°C - Programmable Edge Trigger on Clock - Flow-Through Pinout for Easy PCB Layout APPLICATIONS - Wireless Base Station - Backplane Interconnect - DSLAM DESCRIPTION The SN65LV1023A serializer and SN65LV1224B deserializer prise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock. The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of - 40°C to 85°C. DIN0 SYNC2 SYNC1 DVCC DVCC DVCC DVCC AVCC SYNC1 SYNC2 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 DIN8 DIN9...