SN65LVDS822 Overview
Key Specifications
Package: VQFN
Mount Type: Surface Mount
Pins: 48
Operating Voltage: 3.3 V
Description
The SN65LVDS822 is an advanced FlatLink™ lowvoltage differential signal (LVDS) receiver designed on a modern CMOS process. The device has several unique features, including three selectable CMOS output slew rates, CMOS output voltage support of 1.8 V to 3.3 V, a pinout swap option, integrated differential termination (configurable), an automatic low-power mode, and deserialization modes of 4:27 and 2:27.
Key Features
- 1 4:27 LVDS-to-CMOS Deserializer
- Pixel Clock Range of 4 MHz to 54 MHz, for Resolutions of 160 × 120 to 1024 × 600
- Special 2:27 Mode With 14x Sampling Allows Using Just Two Data Lanes
- Very Low EMI With 3-Way Selectable CMOS Slew Rate
- Supports Single 3.3-V Power Supply; VDDIO Allows 1.8 V to 3.3 V for Flexible Panel Support
