SN65MLVD040 Datasheet | Texas Instruments

Features - Low-Voltage Differential 30Ω to 55Ω Line Drivers and Receivers for Signaling Rates(1) Up to 250Mbps; Clock Frequencies Up to 125MHz - Meets or Exceeds the M-LVDS Standard TIA/ EIA-899 for Multipoint Data Interchange - Controlled Driver Output Voltage Transition Times for Improved Signal Quality - - 1V to 3.4V mon-Mode Voltage Range Allows Data Transfer With 2V of Ground Noise - Bus Pins High Impedance When Driver Disabled or VCC ≤ 1.5V - Independent Enables for each Driver and Receiver - Enhanced ESD Protection: 7k V HBM on all Pins - 48 pin 7 X 7 QFN (RGZ) - M-LVDS Bus Power Up/Down Glitch Free 2 Applications - Parallel Multipoint Data and Clock Transmission Via Backplanes and Cables - Low-Power High-Speed Short-Reach Alternative to TIA/EIA-485 - Cellular Base Stations - Central-Office Switches - Network Switches and Routers 1DE 1D 1FSEN 1R LOGIC DIAGRAM (POSITIVE LOGIC) SN65MLVD 040 Channel 1 1A 1B 1RE PDN 2DE - 4E 3 2D - 4D 3 2FSEN - 4FSEN 3 2R - 4R 3 2RE - 4RE 3 Channels 2 - 4 2A - 4A 2B - 4B A. The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second) 3 Description The SN65MLVD040 provides four half-duplex transceivers for transmitting and receiving Multipoint Low-Voltage Differential Signals in full pliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250Mbps. The driver outputs have been designed to support multipoint buses presenting loads as low as 30Ω and incorporates controlled transition times to allow for stubs off of the backplane transmission line. The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers have thresholds centered about zero with 25m V of hysteresis to prevent output oscillations with loss of input; Type-2 receivers implement a failsafe by using an offset threshold. The x FSEN pins is used to select the Type-1 and Type-2 receiver for each of the...