SN74ALVCH16820 Datasheet | Texas Instruments

FEATURES - Member of the Texas Instruments Widebus™ Family - Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors - Latch-Up Performance Exceeds 250 m A Per JESD 17 - ESD Protection Exceeds JESD 22 - 2000-V Human-Body Model (A114-A) - 200-V Machine Model (A115-A) DESCRIPTION /ORDERING INFORMATION This 10-bit flip-flop is designed for 1.65-V to 3.6-V VCC operation. The flip-flops of the SN74ALVCH16820 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup ponents. OE input does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. SN74ALVCH16820 3.3-V 10-BIT FLIP-FLOP WITH DUAL OUTPUTS AND 3-STATE OUTPUTS SCES035G - JULY 1995 - REVISED OCTOBER 2004 DGG OR DL PACKAGE (TOP VIEW) 1OE 1 1Q1 2 1Q2 3 GND 4 2Q1 5 2Q2 6 VCC 7 3Q1 8 3Q2 9 4Q1 10 GND 11 4Q2 12 5Q1 13 5Q2 14 6Q1 15 6Q2 16 7Q1 17 GND 18 7Q2 19 8Q1 20 8Q2 21 VCC 22 9Q1 23 9Q2 24 GND 25 10Q1 26 10Q2 27 2OE 28 56 CLK 55 D1 54 NC 53 GND 52 D2 51 NC 50 VCC 49 D3 48 NC 47 D4 46 GND 45 NC 44 D5 43 NC 42 D6 41 NC 40 D7 39 GND 38 NC 37 D8 36 NC 35 VCC 34 D9 33 NC 32 GND 31 D10 30 NC 29 NC - No internal connection Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown...