SN74ALVCH16823 Datasheet | Texas Instruments

FEATURES - Member of the Texas Instruments Widebus™ Family - EPIC™ (Enhanced-Performance Implanted CMOS) Submicron Process - ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 p F, R = 0) - Latch-Up Performance Exceeds 250 m A Per JESD 17 - Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors - Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages DESCRIPTION This 18-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH16823 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. The SN74ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock. SN74ALVCH16823 18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS SCES038F - JULY 1995 - REVISED APRIL 2005 DGG OR DL PACKAGE (TOP VIEW) 1CLR 1 1OE 2 1Q1 3 GND 4 1Q2 5 1Q3 6 VCC 7 1Q4 8 1Q5 9 1Q6 10 GND 11 1Q7 12 1Q8 13 1Q9 14 2Q1 15 2Q2 16 2Q3 17 GND 18 2Q4 19 2Q5 20 2Q6 21 VCC 22 2Q7 23 2Q8 24 GND 25 2Q9 26 2OE 27 2CLR 28 56 1CLK 55 1CLKEN 54 1D1 53 GND 52 1D2 51 1D3 50 VCC 49 1D4 48 1D5 47 1D6 46 GND 45 1D7 44 1D8 43 1D9 42 2D1 41 2D2 40 2D3 39 GND 38 2D4 37 2D5 36 2D6 35 VCC 34 2D7 33 2D8 32 GND 31 2D9 30 2CLKEN 29 2CLK A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus...