SN74LV74A-Q1 Datasheet | Texas Instruments

description /ordering information S This dual positive-edge-triggered D-type flip-flop is designed for 2-V to 5.5-V VCC operation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION{ PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING SOIC - D - 40°C to 125°C TSSOP - PW Tape and reel SN74LV74AQDRQ1 Tape and reel SN74LV74AQPWRQ1 LV74A LV74A † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://.ti.. ‡ Package drawings, thermal data, and symbolization are available at http://.ti./packaging. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. - POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright  2008, Texas Instruments Incorporated 1 SN74LV74A-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP SCLS556B - DECEMBER 2003 - REVISED APRIL 2008 FUNCTION TABLE INPUTS OUTPUTS PRE CLR...