SN74LV8T574 Datasheet | Texas Instruments

Features - Wide operating range of 1.65V to 5.5V - 5.5V tolerant input pins - Single-supply voltage translator (refer to LVx T Enhanced Input Voltage): - Up translation: - 1.2V to 1.8V - 1.5V to 2.5V - 1.8V to 3.3V - 3.3V to 5.0V - Down translation: - 5.0V, 3.3V, 2.5V to 1.8V - 5.0V, 3.3V to 2.5V - 5.0V to 3.3V - Up to 150Mbps with 5V or 3.3V VCC - Supports standard function pinout - Latch-up performance exceeds 250m A per JESD 17 - Supports defense and aerospace applications: - Controlled baseline - One assembly and test site - One fabrication site - Extended product life cycle - Product traceability 2 Applications - Parallel data synchronization - Parallel data storage - Shift register - Pattern generators 3 Description The SN74LV8T574 contains eight D-type flip-flops. All channels share a latch enable (LE) input and output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing. The input is designed with a reduced threshold circuit to support up translation when the supply voltage is larger than the input voltage. Additionally, the 5V tolerant input pins enable down translation when the input voltage is larger than the supply voltage. The output level is always referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. PART NUMBER SN74LV8T574 Device Information PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3) PW (TSSOP, 20) 6.5mm × 6.4mm 6.5mm x 4.4mm DGS (VSSOP, 20) 5.1mm × 4.9mm 5.1mm × 3.0mm RKS (VQFN, 20) 4.5mm × 2.5mm 4.5mm × 2.5mm (1) For more information, see Section 11. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) The body size (length × width) is a nominal value and does not include pins. Shared Control...