SN74SSQE32882
FEATURES
- 2 JEDEC SSTE32882 pliant
- 1-to-2 Register Outputs and 1-to-4 Clock Pair
Outputs Support Stacked DDR3 DIMMs
- Chip Select Inputs Prevent Data Outputs from
Changing State and Minimize System Power Consumption
- 1.5-V Phase Lock Loop Clock Driver Buffers One Differential Clock Pair (CK and CK) and Distributes to Four Differential Outputs
- 1.5-V CMOS Inputs
- Checks Parity on mand and Address (CS-gated) Data Inputs
- Supports LVCMOS Switching Levels on RESET Input
- RESET Input:
- Disables Differential Input Receivers
- Resets All Registers
- Forces All Outputs into Pre-defined States
- Optimal Pinout for DDR3 DIMM PCB Layout
- Supports Four Chip Selects
- Single Register Backside Mount Support
APPLICATIONS
- DDR3 Registered DIMMs up to DDR3-1333
- Single-, Dual- and Quad-Rank RDIMM
DESCRIPTION
/ORDERING INFORMATION
This JEDEC SSTE32882-pliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 Registered DIMMs up to...
