SN74SSQE32882 Overview
All inputs are 1.5-V, CMOS-patible. All outputs are 1.5-V CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. Clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn, and DxODTn can each be driven with a different strength and skew to optimize signal integrity, pensate for different loading, and balance signal travel speed.
SN74SSQE32882 Key Features
- 2 JEDEC SSTE32882 pliant
- 1-to-2 Register Outputs and 1-to-4 Clock Pair
- Chip Select Inputs Prevent Data Outputs from
- 1.5-V Phase Lock Loop Clock Driver Buffers One Differential Clock Pair (CK and CK) and Distributes to Four Differential
- 1.5-V CMOS Inputs
- Checks Parity on mand and Address (CS-gated) Data Inputs
- Supports LVCMOS Switching Levels on RESET Input
- RESET Input
- Disables Differential Input Receivers
- Resets All Registers
SN74SSQE32882 Applications
- DDR3 Registered DIMMs up to DDR3-1333