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SN74SSQE32882 - 28-BIT TO 56-BIT REGISTERED BUFFER

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Overview

SN74SSQE32882 www.ti.com .................................................................................................................................................

Key Features

  • 1.
  • 2 JEDEC SSTE32882 Compliant.
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 DIMMs.
  • Chip Select Inputs Prevent Data Outputs from Changing State and Minimize System Power Consumption.
  • 1.5-V Phase Lock Loop Clock Driver Buffers One Differential Clock Pair (CK and CK) and Distributes to Four Differential Outputs.
  • 1.5-V CMOS Inputs.
  • Checks Parity on Command and Address (CS-gated) Data Inputs.
  • Supports LVCMOS.

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