SN74SSQEC32882 Overview
All inputs are 1.5 V, 1.35V and 1.25 V CMOS patible. All outputs are CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn and Yn and control net outputs DxCKEn, DxCSn and DxODTn can be driven with a different strength and skew to optimize signal integrity, pensate for different loading and equalize signal travel speed.
SN74SSQEC32882 Key Features
- JEDEC SSTE32882
- 1-to-2 Register Outputs and 1-to-4 Clock Pair
- CKE Powerdown Mode for Optimized System
- 1.5V/1.35V/1.25V Phase Lock Loop Clock
- 1.5V/1.35V/1.25V CMOS Inputs
- Checks Parity on mand and Address
- Configurable Driver Strength
- Uses Internal Feedback Loop
- Optimized Power Consumption
SN74SSQEC32882 Applications
- DDR3 Registered DIMMs up to DDR3-1866
- DDR3L Registered DIMMs up to DDR3L-1600
- DDR3U Registered DIMMs up to DDR3U-1333