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SN74SSQEC32882 - 28-Bit to 56-Bit Registered Buffer

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Overview

SN74SSQEC32882 www.ti.com SCAS920-PUB – NOVEMBER 2011 28-Bit to 56-Bit Registered Buffer With Address Parity Test One Pair to Four Pair Differential Clock PLL Driver Check for Samples:.

Key Features

  • 1.
  • JEDEC SSTE32882.
  • 1-to-2 Register Outputs and 1-to-4 Clock Pair Outputs Support Stacked DDR3 RDIMMs.
  • CKE Powerdown Mode for Optimized System Power Consumption.
  • 1.5V/1.35V/1.25V Phase Lock Loop Clock Driver for Buffering One Differential Clock Pair (CK and CK) and Distributing to Four Differential Outputs.
  • 1.5V/1.35V/1.25V CMOS Inputs.
  • Checks Parity on Command and Address (CS-Gated) Data Inputs.
  • Configurable Driver Strength.

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