TPIC6B596 Datasheet | Texas Instruments

description DW OR N PACKAGE (TOP VIEW) NC 1 VCC 2 SER IN 3 DRAIN0 4 DRAIN1 5 DRAIN2 6 DRAIN3 7 SRCLR 8 G9 GND 10 20 NC 19 GND 18 SER OUT 17 DRAIN7 16 DRAIN6 15 DRAIN5 14 DRAIN4 13 SRCK 12 RCK 11 GND The TPIC6B596 is a monolithic, high-voltage, - No internal connection medium-current power 8-bit shift register designed for use in systems that require relatively logic symbol† high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications G9 RCK 12 EN3 C2 include relays, solenoids, and other mediumcurrent or high-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shiftregister clear (SRCLR) is high. When SRCLR is low, all registers in the device are cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage 8 SRCLR 13 SRCK SRG8 R C1 SER IN 3 1D 4 DRAIN0 5 DRAIN1 6 DRAIN2 7 DRAIN3 14 DRAIN4 15 DRAIN5 16 DRAIN6 17 DRAIN7 18 SER OUT register is transparent to the output buffers. When data in the output buffers is low, the DMOS- † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. transistor outputs are off. When data is high, the DMOS-transistor outputs have sink-current capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. Outputs are low-side,...