Datasheet4U Logo Datasheet4U.com

74LVC16373A - 16-bit D-type transparent latch

Description

The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches with 3-state outputs.

The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch.

Features

  • Overvoltage tolerant inputs to 5.5 V.
  • Wide supply voltage range from 1.2 V to 3.6 V.
  • CMOS low power dissipation.

📥 Download Datasheet

Datasheet preview – 74LVC16373A

Datasheet Details

Part number 74LVC16373A
Manufacturer nexperia
File Size 256.75 KB
Description 16-bit D-type transparent latch
Datasheet download datasheet 74LVC16373A Datasheet
Additional preview pages of the 74LVC16373A datasheet.

📁 Similar Datasheet

  • 74LVC16374A - 16-bit edge triggered D-type flip-flop (Philips)
  • 74LVC163 - Presettable synchronous 4-bit binary counter (Philips)
  • 74LVC161 - Presettable synchronous 4-bit binary counter (Philips)
  • 74LVC161284 - 19-BIT BUS INTERFACE (Texas Instruments)
  • 74LVC161284 - LOW VOLTAGE HIGH SPEED IEEE1284 TRANSCEIVER (ST Microelectronics)
  • 74LVC162245A - 16-bit transceiver (Philips)
  • 74LVC162373A - 16-bit D-type transparent latch (Philips)
  • 74LVC162374A - 16-bit edge triggered D-type flip-flop (Philips)
  • 74LVC16240A - 16-bit buffer/line driver (Philips)
  • 74LVC16244A - 16-bit buffer/line driver (NXP Semiconductors)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 10 — 1 October 2021 Product data sheet 1. General description The 74LVC16373A and 74LVCH16373A are 16-bit D-type transparent latches with 3-state outputs. The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE.
Published: |