Description
configuration, in which a normally-on SiC JFET is co-packaged with a Si MOSFET to produce a normally-off SiC FET device.
Features
- Typical On-resistance RDS(on),typ of 42 mW.
- Maximum Operating Temperature of 175°C.
- Excellent Reverse Recovery.
- Low Gate Charge.
- Low Intrinsic Capacitance.
- ESD Protected, HBM Class 2.
- Very Low Switching Losses (Required RC-snubber Loss Negligible
under Typical Operating Conditions).
- This Device is Halogen Free and RoHS Compliant with Exemption
7a, Pb.
- Free 2LI (on second level interconnection)
Typical.
UF3C065040B3 Datasheet
