| Part Number | 74LS73A Datasheet |
|---|---|
| Manufacturer | Hitachi Semiconductor |
| Overview | Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0.10 Hitachi Code JEDEC EIAJ Weight (reference val. rty rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be su. |
74LS73A Datasheet and Specifications PDF
The 74LS73A is a Dual J-K Flip-Flops.
| Part Number | 74LS73A Datasheet |
|---|---|
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops |
| Manufacturer | Fairchild Semiconductor |
| Overview | This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The cloc. uit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs CLR L H H H H H CLK X ↓ ↓ ↓ ↓ H J X L H L. |