| Part Number | S5933QE Datasheet |
|---|---|
| Manufacturer | Unknown Manufacturer |
| Overview | : When performing a bus master write to the PCI bus, if only one location of the FIFO remains full, the S5933 deasasserts FRAME# on the next clock to indicate the last data phase is in progress. If an. . If another value is written from the add-on at the right moment, an internal condition may cause IRDY# to remain asserted to sustain the burst, but FRAME# has already been dasserted. Workaround: Externally synchronizing WRFIFO# or WR# to BPCLK moves the rising edge of the write strobe to prevent t. |
S5933QE Datasheet and Specifications PDF
The S5933QE is a Controller Device Summary.
Key Specifications
| Package | QFP |
|---|---|
| Operating Voltage | 5 V |
| Max Voltage (typical range) | 5.25 V |
| Min Voltage (typical range) | 4.75 V |
| Max Frequency | 33.33 MHz |
| Length | 28 mm |
| Width | 28 mm |
| Max Operating Temp | 70 °C |
| Part Number | S5933QE Datasheet |
|---|---|
| Description | PCI Interface Device Summary |
| Manufacturer | AMCC |
| Overview | When performing a bus master write to the PCI bus, if only one location of the FIFO remains full, the S5933 deasserts FRAME# on the next clock to indicate the last data phase is in progress. If anoth. o sustain the burst, but FRAME# has already been deasserted. Workaround: Externally synchronizing WRFIFO# or WR# to BPCLK moves the rising edge of the write strobe to prevent this event from occurring. Request separate D8 applications note from your local FAE or Insight TSE for more detail. Status: . |