1-MBit Datasheet | Specifications & PDF Download

25Q16BSIG FEATURES ◆ 16M-bit Serial Flash -2048K-byte -256 bytes per programmable page ◆ Standard, Dual, Quad SPI -Standard SPI: SCLK, CS#, SI, SO, W

(41 views)

36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

(36 views)

512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus Interface Pm25LD512/010/ 020 FEATURES • Single

(33 views)

CY7C25422KV18 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 72-Mbit QDR® II+ SRAM Two-Word Burst Architecture (

(30 views)

CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features • Separate independ

(30 views)

36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

(29 views)

CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features • Separate independ

(28 views)

CY7C2262XV18/CY7C2264XV18 36-Mbit QDR® II+ Xtreme SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 36-Mbit QDR® II+ Xtreme SRAM Two

(27 views)

www.datasheet4u.com April 2007 HYB25DC512800B[E/F] HYB25DC512160B[E/F] 512-Mbit Double-Data-Rate SDRAM DDR SDRAM RoHS Compliant Products Internet

(27 views)

Module Features • • • • 128-Mbit Burst/Page Flash + 32-Mbit/64-Mbit PSRAM Single 88-ball (8 mm x 10 mm x 1.2 mm) CBGA Package 1.7V to 1.95V VCC 1.8V t

(27 views)

36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

(27 views)

HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DESCRIPTION The 6N137, HCPL-2601/2611 single-channel and HCPL-26

(26 views)

CY7C25632KV18 CY7C25652KV18 72-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 72-Mbit QDR® II+ SRAM Four-Word Burs

(26 views)

M29F010B 1 Mbit (128Kb x8, Uniform Block) Single Supply Flash Memory PRELIMINARY DATA s SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPER

(26 views)

Data Sheet June 1999 www.DataSheet4U.com CDRM622 622 Mbits/s Multichannel Digital Timing Recovery Features s Description The CDRM622 provides a phys

(26 views)

36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C

(26 views)

HIGH SPEED-10 MBit/s LOGIC GATE OPTOCOUPLERS SINGLE-CHANNEL 6N137 HCPL-2601 HCPL-2611 DESCRIPTION The 6N137, HCPL-2601/2611 single-channel and HCPL-26

(25 views)

CY7C1618KV18/CY7C1620KV18 144-Mbit DDR II SRAM Two-Word Burst Architecture 144-Mbit DDR II SRAM Two-Word Burst Architecture Features ■ 144-Mbit densi

(25 views)

CY7C1526KV18 CY7C1513KV18 CY7C1515KV18 72-Mbit QDR® II SRAM Four-Word Burst Architecture 72-Mbit QDR® II SRAM Four-Word Burst Architecture Features ■

(25 views)

CY7C1522JV18, CY7C1529JV18 CY7C1523JV18, CY7C1524JV18 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture Features ■ ■ ■ ■ ■ Functional Description Th

(25 views)