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CY7C1245KV18

36-Mbit QDR II SRAM 4-Word Burst Architecture

CY7C1245KV18 Features

* Configurations With Read Cycle Latency of 2.0 cycles: CY7C1241KV18

* 4 M × 8 CY7C1256KV18

* 4 M × 9 CY7C1243KV18

* 2 M × 18 CY7C1245KV18

* 1 M × 36 Separate independent read and write data ports

* Supports concurrent transactions 450 MHz clock for high ban

CY7C1245KV18 General Description


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* Functional Description The CY7C1241KV18, CY7C1256KV18, CY7C1243KV18, and CY7C1245KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the .

CY7C1245KV18 Datasheet (Direct Link)

Preview of CY7C1245KV18 PDF

Datasheet Details

Part number:

CY7C1245KV18

Manufacturer:

Cypress Semiconductor

File Size:

Direct Link

Description:

36-mbit qdr ii sram 4-word burst architecture.
36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) CY7C.

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TAGS

CY7C1245KV18 36-Mbit QDR SRAM 4-Word Burst Architecture Cypress Semiconductor

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