CY7C1245KV18 - 36-Mbit QDR II SRAM 4-Word Burst Architecture
* * * * * Functional Description The CY7C1241KV18, CY7C1256KV18, CY7C1243KV18, and CY7C1245KV18 are 1.8 V synchronous pipelined SRAMs, equipped with QDR II+ architecture.
Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the read port and the
CY7C1245KV18 Features
* Configurations With Read Cycle Latency of 2.0 cycles: CY7C1241KV18
* 4 M × 8 CY7C1256KV18
* 4 M × 9 CY7C1243KV18
* 2 M × 18 CY7C1245KV18
* 1 M × 36 Separate independent read and write data ports
* Supports concurrent transactions 450 MHz clock for high ban
