128K-Bit Datasheet | Specifications & PDF Download

® LY62L1024 Rev. 1.2 128K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Description Initial Issue Revised Icc De

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FM24C128 – 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM FM24C128 – 128K-Bit Standard 2-Wire Bus Interface Serial EEPROM December 2001 Gener

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® LY611024 Rev. 1.4 128K X 8 BIT HIGH SPEED CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.4 Description Initial Is

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® LY61L1024 Rev. 2.2 128K X 8 BIT HIGH SPEED CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 2.0 Rev. 2.1 Rev.2.2 Description Initial Is

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LP621024D Series 128K X 8 BIT CMOS SRAM Features n Single +5V power supply n Access times: 55/70 ns (max.) n Current: Very low power version: Operatin

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LP62S16128B-T Series 128K X 16 BIT LOW VOLTAGE CMOS SRAM Features n Operating voltage: 2.7V to 3.6V n Access times: 55/70 ns (max.) n Current: Very lo

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GT25C128 GT25C128 SPI 128K Bits Serial EEPROM Copyright © 2011 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right

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ACT-S128K32V High Speed 3.3Volt 4 Megabit SRAM Multichip Module Features s 4 Low Power CMOS 128K x 8 SRAMs in one MCM s Overall configuration as 128K

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HY628100B Series 128Kx8bit CMOS SRAM Document Title 128K x8 bit 5.0V Low Power CMOS slow SRAM Revision History Revision No 10 11 History Initial Rev

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PRELIMINARY K6R1008C1B-C, K6R1008C1B-I Document Title 128Kx8 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out. Operated at Commercial an

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 UTRON Rev. 1.7 FEATURES „ „ UT62L1024 128K X 8 BIT LOW POWER CMOS SRAM GENERAL DESCRIPTION The UT62L1024 is a 1,048,576-bit low power CMOS static

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1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY 28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B Y High-Integration Blocked Architecture One 8 KB Boot Block w L

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1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY 28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B Y High-Integration Blocked Architecture One 8 KB Boot Block w L

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1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY 28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B Y High-Integration Blocked Architecture One 8 KB Boot Block w L

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DATA SHEET µ PD431000A-X 1M-BIT CMOS STATIC RAM 128K-WORD BY 8-BIT EXTENDED TEMPERATURE OPERATION MOS INTEGRATED CIRCUIT Description The µPD431000A

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CY62137VN MoBL® 2-Mbit (128K x 16) Static RAM Features • Temperature Ranges — Industrial: –40°C to 85°C — Automotive-A: –40°C to 85°C — Automotive-E:

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OKI ML2502 RECORD/PLAYBACK LSI with 128Kbit Analog Cell Storage Flash Memory n ML2502 DATA SHEET Preliminary Revision 8.0 Apr. 01, 1999 GENERAL D

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1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY 28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B Y High-Integration Blocked Architecture One 8 KB Boot Block w L

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NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM October 1998 NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM General Des

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M29F200BT M29F200BB 2 Mbit (256Kb x8 or 128Kb x16, Boot Block) Single Supply Flash Memory PRELIMINARY DATA s SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM

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