128K-Bit Datasheet | Specifications & PDF Download

Features • Single Supply for Read and Write: 2.7 to 3.6V • Fast Read Access Time – 55 ns • Internal Program Control and Timer • Sector Architecture –

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M29F200BT M29F200BB 2 Mbit (256Kb x8 or 128Kb x16, Boot Block) Single Supply Flash Memory PRELIMINARY DATA s SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM

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® LY62L1024 Rev. 1.2 128K X 8 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Description Initial Issue Revised Icc De

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A62S7308B Series Preliminary 128K X 8 BIT LOW VOLTAGE CMOS SRAM Document Title 128K X 8 BIT LOW VOLTAGE CMOS SRAM Revision History Rev. No. 0.0 0

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M29F010B 1 Mbit (128Kb x8, Uniform Block) Single Supply Flash Memory PRELIMINARY DATA s SINGLE 5V±10% SUPPLY VOLTAGE for PROGRAM, ERASE and READ OPER

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1-MBIT (128K x 8) BOOT BLOCK FLASH MEMORY 28F001BX-T 28F001BX-B 28F001BN-T 28F001BN-B Y High-Integration Blocked Architecture One 8 KB Boot Block w L

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www.DataSheet4U.com PDM41024 1 Megabit Static RAM 128K x 8-Bit Features n 1 2 3 4 5 6 7 Description The PDM41024 is a high-performance CMOS static

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Features • Fast Read Access Time – 120 ns • Automatic Page Write Operation – Internal Address and Data Latches for 128 Bytes – Internal Control Timer

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AT29C010A Features • • • • • • • • • • • • • Fast Read Access Time - 70 ns 5-Volt-Only Reprogramming Sector Program Operation Single Cycle Reprogram

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® LY6212816 Rev. 1.3 128K X 16 BIT LOW POWER CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Description Initial Issue Added -45 ns

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NEe NEe Microcomputers, Inc. }LPD23128 ~rn~[~~~~ffirnW FULLY DECODED 128K BIT MASK PROGRAMMABLE READ ONLY MEMORY OESCR I PTION The NEC IlPD23128

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AT27C010/L Features • • • • • • • • • Fast Read Access Time - 45 ns Low Power CMOS Operation 100 µA max. Standby 25 mA max. Active at 5 MHz (AT27C01

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PRELIMINARY MX28F2100B 2M-BIT [256K x 8/128K x 16] CMOS FLASH MEMORY FEATURES • 262,144x8/131,072x16 switchable • Fast access time: 70/90/120ns • Low

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GT24C128 Advanced GT24C128 2-WIRE 128K Bits Serial EEPROM (Not Recommended for New Design) Copyright © 2011 Giantec Semiconductor Inc. (Giantec).

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BL24C128A 128K bits (16,384×8) Features ⚫ Compatible with all I2C bidirectional data transfer protocol – 1 MHz – 400 kHz – 100 kHz ⚫ Memory array: –

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® LY6112816 Rev. 1.1 5V 128K X 16 BIT HIGH SPEED CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Description Initial Issue Revised Test Condi

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LP621024D Series 128K X 8 BIT CMOS SRAM Features n Single +5V power supply n Access times: 55/70 ns (max.) n Current: Very low power version: Operatin

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MX27C1000 1M-BIT [128K x 8] CMOS EPROM FEATURES • • • • • • 128K x 8 organization Single +5V power supply +12.5V programming voltage Fast access tim

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® LY61L1024 Rev. 2.2 128K X 8 BIT HIGH SPEED CMOS SRAM REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 2.0 Rev. 2.1 Rev.2.2 Description Initial Is

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