74AC Datasheet | Specifications & PDF Download

74AC163 • 74ACT163 Synchronous Presettable Binary Counter November 1988 Revised February 2000 74AC163 • 74ACT163 Synchronous Presettable Binary Coun

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TECHNICAL DATA Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS The IN74AC373 is identical in pinout to the LS/ALS373, HC/HC

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TECHNICAL DATA IN74ACT374 Octal 3-State Noninverting D Flip-Flop High-Speed Silicon-Gate CMOS The IN74ACT374 is identical in pinout to the LS/ALS374

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74AC00, 74ACT00 — Quad 2-Input NAND Gate January 2008 74AC00, 74ACT00 Quad 2-Input NAND Gate Features ■ ICC reduced by 50% ■ Outputs source/sink 24m

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TECHNICAL DATA IN74AC253 Dual 4-Input Data Selector/Multiplexer with 3-State Otputs High-Speed Silicon-Gate CMOS The IN74AC253 is identical in pinou

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74AC520, 74ACT520 8-Bit Identity Comparator 74AC520, 74ACT520 8-Bit Identity Comparator Features ■ Compares two 8-bit words in 6.5ns typ. ■ Expandabl

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TECHNICAL DATA Quad 2-Input OR Gate High-Speed Silicon-Gate CMOS The IN74AC32 is identical in pinout to the LS/ALS32, HC/HCT32. The device inputs are

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TECHNICAL DATA IN74ACT10 Triple 3-Input NAND Gate High-Speed Silicon-Gate CMOS The IN74ACT10 is identical in pinout to the LS/ALS10, HC/HCT10. The I

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TECHNICAL DATA IN74ACT34 Hex Noninverter Buffer High-Speed Silicon-Gate CMOS The IN74ACT34 is identical in pinout to the LS/ALS34, HC/HCT34. The IN7

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TC74ACT299P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT299P, TC74ACT299F 8-Bit PIPO Shift Register with Asynchronous Clear

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ą • Local Bus-Latch Capability • Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configura

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HD74ACT161/HD74ACT163 Synchronous Presettable Binary Counter Description The HD74ACT161 and HD74ACT163 are high-speed synchronous modulo-16 binary co

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HD74AC165/HD74ACT165 Parallel-Load 8-bit Shift Register Description This 8-bit serial shift register shifts data from Q A to QH when clocked, Paralle

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74AC11008 QUADRUPLE 2-INPUT POSITIVE-AND GATE D Flow-Through Architecture Optimizes PCB Layout D Center-Pin VCC and GND Configurations Minimize High-

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ą • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise • EPIC (Enhanced-Perfo

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74AC11138 3ĆLINE TO 8ĆLINE DECODER/DEMULTIPLEXER D Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems D Incorporates

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74ACT16543 16-Bit Registered Transceiver with 3-STATE Outputs August 1999 Revised October 1999 74ACT16543 16-Bit Registered Transceiver with 3-STATE

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74ACT16646 16-Bit Transceiver/Register with 3-STATE Outputs August 1999 Revised October 1999 74ACT16646 16-Bit Transceiver/Register with 3-STATE Out

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74ACT20 DUAL 4-INPUT NAND GATE s s s s s s s s s HIGH SPEED: tPD = 5ns (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C CO

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54AC253 • 54ACT253 Dual 4-Input Multiplexer with TRI-STATE Outputs August 1998 54AC253 • 54ACT253 Dual 4-Input Multiplexer with TRI-STATE ® Outputs

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