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74ACT11109 - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

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54ACT11109 .

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54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 • Inputs Are TTL-Voltage Compatible • Flow-Through Architecture Optimizes PCB Layout • Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise • EPIC™ (Enhanced-Performance Implanted CMOS) 1-µm Process • 500-mA Typical Latch-Up Immunity at 125°C • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs description 54ACT11109 . . . J PACKAGE 74ACT11109 . . . D OR N PACKAGE (TOP VIEW) 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2CLK 1 2 3 4 5 6 7 8 16 1CLK 15 1K 14 1J 13 1CLR 12 VCC 11 2CLR 10 2J 9 2K 54ACT11109 . . .