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74ACT11139 DUAL 2ĆLINE TO 4ĆLINE DECODER/DEMULTIPLEXER
D Inputs Are TTL-Voltage Compatible D Designed Specifically for High-Speed
Memory Decoders and Data Transmission Systems
D Incorporates Two Enable Inputs to Simplify
Cascading and/or Data Reception
D Fully Synchronous Operation for Counting D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)
SCAS175A − SEPTEMBER 1991 − REVISED APRIL 1996
D, N, OR PW PACKAGE (TOP VIEW)
1Y1 1 1Y2 2 1Y3 3 GND 4 2Y0 5 2Y1 6 2Y2 7 2Y3 8
16 1Y0 15 1A 14 1B 13 1G 12 VCC 11 2G 10 2A 9 2B
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