Datasheet Summary
74ACT11139 DUAL 2ĆLINE TO 4ĆLINE DECODER/DEMULTIPLEXER
D Inputs Are TTL-Voltage patible D Designed Specifically for High-Speed
Memory Decoders and Data Transmission Systems
D Incorporates Two Enable Inputs to Simplify
Cascading and/or Data Reception
D Fully Synchronous Operation for Counting D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (D) and Thin Shrink Small-Outline (PW) Packages, and Standard Plastic 300-mil DIPs (N)
SCAS175A
- SEPTEMBER 1991
- REVISED APRIL 1996
D, N, OR PW PACKAGE (TOP VIEW)
1Y1 1...