DPLL Datasheet | Specifications & PDF Download

Data Sheet Quad Input, 10-Output, Dual DPLL/IEEE 1588 Synchronizer and Jitter Cleaner AD9543 FEATURES Dual DPLL synchronizes 2 kHz to 750 MHz physic

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ZL30110 Telecom Rate Conversion DPLL Features • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz • Provides a range of output clocks: • 65.5

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Features • Supports requirements of ITU-T G.8262 for Synchronous Ethernet Equipment Slave Clocks (EEC option 1 and 2) • Supports requirements of Telco

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ZL30106 SONET/SDH/PDH Network Interface DPLL Data Sheet Features • Synchronizes to clock-and-sync-pair to maintain minimal phase skew between inputs

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www.DataSheet4U.com DataSheet4U.com DataSh ee DataSheet4U.com DataSheet 4 U .com www.DataSheet4U.com m et4U.co DataSheet4U.com DataSh ee Da

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ZL30112 SLIC/CODEC DPLL Data Sheet Features November 2009 • Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 19.44 MHz input • Provides 2.048 MHz an

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Features • Supports output wander and jitter generation specifications for GR-253-CORE OC-3 and G.813 STM-1 SONET/SDH interfaces • Accepts two input r

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ABRIDGED DATA SHEET www.DataSheet4U.com 19-5256; Rev 0; 4/10 DS31400 8-Input, 14-Output, Dual DPLL Timing IC with Sub-ps Output Jitter General Descr

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ABRIDGED DATA SHEET 19-5710; Rev 0; 12/10 DS31404 4-Input, 8-Output, Dual DPLL Timing IC with Sub-ps Output Jitter General Description The DS31404 is

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ABRIDGED DATA SHEET 19-5711; Rev 0; 12/10 DS31406 2-Input, 14-Output, Single DPLL Timing IC with Sub-ps Output Jitter General Description The DS31406

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Features • Supports requirements of ITU-T G.8262 for Synchronous Ethernet Equipment Slave Clocks (EEC option 1 and 2) • Supports requirements of Telco

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